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elpida memory, inc. is a joint venture dram company of nec corporation and hitachi, ltd. hm5259165b-75/a6 hm5259805b-75/a6 hm5259405b-75/a6 512m lvttl interface sdram 133 mhz/100 mhz 8-mword 16-bit 4-bank/16-mword 8-bit 4-bank /32-mword 4-bit 4-bank pc/133, pc/100 sdram e0118h10 ver. 1.0 apr. 6, 2001 description the hm5259165b is a 512-mbit sdram organized as 8388608-word 16-bit 4 bank. the hm5259805b is a 512-mbit sdram organized as 16777216-word 8-bit 4 bank. the hm5259405b is a 512-mbit sdram organized as 33554432-word 4-bit 4 bank. all inputs and outputs are referred to the rising edge of the clock input. it is packaged in standard 54-pin plastic tsop ii. features ? 3.3 v power supply ? clock frequency: 133 mhz/100 mhz (max) ? lvttl interface ? single pulsed ras ? 4 banks can operate simultaneously and independently ? burst read/write operation and burst read/single write operation capability ? programmable burst length: 1/2/4/8 ? 2 variations of burst sequence ? sequential (bl = 1/2/4/8) ? interleave (bl = 1/2/4/8)
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 2 ? programmable cas latency: 2/3 ? byte control by dqm : dqm (hm5259805b/hm5259405b) : dqmu/dqml (hm5259165b) ? refresh cycles: 8192 refresh cycles/32 ms ? 2 variations of refresh ? auto refresh ? self refresh ordering information type no. frequency cas latency package hm5259165btd-75* 1 hm5259165btd-a6 133 mhz 100 mhz 3 2/3 400-mil 54-pin plastic tsop ii (ttp-54da) hm5259805btd-75* 1 hm5259805btd-a6 133 mhz 100 mhz 3 2/3 hm5259405btd-75* 1 hm5259405btd-a6 133 mhz 100 mhz 3 2/3 notes: 1. 100 mhz operation at cas latency = 2
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 3 pin arrangement (hm5259165b) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 v ss dq15 v ss q dq14 dq13 v cc q dq12 dq11 v ss q dq10 dq9 v cc q dq8 v ss nc dqmu clk cke a12 a11 a9 a8 a7 a6 a5 a4 v ss v cc dq0 v cc q dq1 dq2 v ss q dq3 dq4 v cc q dq5 dq6 v ss q dq7 v cc dqml we cas ras cs ba0 ba1 a10 a0 a1 a2 a3 v cc 54-pin tsop (top view) pin description pin name function pin name function a0 to a12, ba0, ba1 address input we write enable ? row address a0 to a12 dqmu/dqml input/output mask ? column address a0 to a9 clk clock input ? bank select address ba0/ba1 (bs) cke clock enable dq0 to dq15 data-input/output v cc power for internal circuit cs chip select v ss ground for internal circuit ras row address strobe command v cc q power for dq circuit cas column address strobe command v ss q ground for dq circuit nc no connection
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 4 pin arrangement (hm5259805b) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 v ss dq7 v ss q nc dq6 v cc q nc dq5 v ss q nc dq4 v cc q nc v ss nc dqm clk cke a12 a11 a9 a8 a7 a6 a5 a4 v ss v cc dq0 v cc q nc dq1 v ss q nc dq2 v cc q nc dq3 v ss q nc v cc nc we cas ras cs ba0 ba1 a10 a0 a1 a2 a3 v cc 54-pin tsop (top view) pin description pin name function pin name function a0 to a12, ba0, ba1 address input we write enable ? row address a0 to a12 dqm input/output mask ? column address a0 to a9, a11 clk clock input ? bank select address ba0/ba1 (bs) cke clock enable dq0 to dq7 data-input/output v cc power for internal circuit cs chip select v ss ground for internal circuit ras row address strobe command v cc q power for dq circuit cas column address strobe command v ss q ground for dq circuit nc no connection
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 5 pin arrangement (hm5259405b) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 v ss nc v ss q nc dq3 v cc q nc nc v ss q nc dq2 v cc q nc v ss nc dqm clk cke a12 a11 a9 a8 a7 a6 a5 a4 v ss v cc nc v cc q nc dq0 v ss q nc nc v cc q nc dq1 v ss q nc v cc nc we cas ras cs ba0 ba1 a10 a0 a1 a2 a3 v cc 54-pin tsop (top view) pin description pin name function pin name function a0 to a12, ba0, ba1 address input we write enable ? row address a0 to a12 dqm input/output mask ? column address a0 to a9, a11 a12 clk clock input ? bank select address ba0/ba1 (bs) cke clock enable dq0 to dq3 data-input/output v cc power for internal circuit cs chip select v ss ground for internal circuit ras row address strobe command v cc q power for dq circuit cas column address strobe command v ss q ground for dq circuit nc no connection
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 6 block diagram (hm5259165b) column address counter column address buffer upper pellet lower pellet row address buffer refresh counter column address counter column address buffer row address buffer refresh counter dq8 to dq15 dq0 to dq7 input buffer output buffer control logic & timing generator row decoder sense amplifier & i/o bus column decoder clk cke cs ras cas we dqmu /dqml a0 to a9 row decoder sense amplifier & i/o bus column decoder row decoder sense amplifier & i/o bus column decoder row decoder row decoder row decoder row decoder row decoder sense amplifier & i/o bus column decoder memory array bank0 8192 row 1024 column 8 bit memory array bank1 8192 row 1024 column 8 bit memory array bank2 8192 row 1024 column 8 bit memory array bank3 8192 row 1024 column 8 bit sense amplifier & i/o bus column decoder sense amplifier & i/o bus column decoder sense amplifier & i/o bus column decoder sense amplifier & i/o bus column decoder memory array bank0 8192 row 1024 column 8 bit memory array bank1 8192 row 1024 column 8 bit memory array bank2 8192 row 1024 column 8 bit memory array bank3 8192 row 1024 column 8 bit input buffer output buffer a0 to a12, ba0, ba1 a0 to a12, ba0, ba1
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 7 block diagram (hm5259805b) column address counter column address buffer upper pellet lower pellet row address buffer refresh counter column address counter column address buffer row address buffer refresh counter dq4 to dq7 dq0 to dq3 input buffer output buffer control logic & timing generator row decoder sense amplifier & i/o bus column decoder clk cke cs ras cas we dqm a0 to a9, a11 row decoder sense amplifier & i/o bus column decoder row decoder sense amplifier & i/o bus column decoder row decoder row decoder row decoder row decoder row decoder sense amplifier & i/o bus column decoder memory array bank0 8192 row 2048 column 4 bit memory array bank1 8192 row 2048 column 4 bit memory array bank2 8192 row 2048 column 4 bit memory array bank3 8192 row 2048 column 4 bit sense amplifier & i/o bus column decoder sense amplifier & i/o bus column decoder sense amplifier & i/o bus column decoder sense amplifier & i/o bus column decoder memory array bank0 8192 row 2048 column 4 bit memory array bank1 8192 row 2048 column 4 bit memory array bank2 8192 row 2048 column 4 bit memory array bank3 8192 row 2048 column 4 bit input buffer output buffer a0 to a12, ba0, ba1 a0 to a12, ba0, ba1
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 8 block diagram (hm5259405b) column address counter column address buffer upper pellet lower pellet row address buffer refresh counter column address counter column address buffer row address buffer refresh counter dq2 to dq3 dq0 to dq1 input buffer output buffer control logic & timing generator row decoder sense amplifier & i/o bus column decoder clk cke cs ras cas we dqm row decoder sense amplifier & i/o bus column decoder row decoder sense amplifier & i/o bus column decoder row decoder row decoder row decoder row decoder row decoder sense amplifier & i/o bus column decoder memory array bank0 8192 row 4096 column 2 bit memory array bank1 8192 row 4096 column 2 bit memory array bank2 8192 row 4096 column 2 bit memory array bank3 8192 row 4096 column 2 bit sense amplifier & i/o bus column decoder sense amplifier & i/o bus column decoder sense amplifier & i/o bus column decoder sense amplifier & i/o bus column decoder memory array bank0 8192 row 4096 column 2 bit memory array bank1 8192 row 4096 column 2 bit memory array bank2 8192 row 4096 column 2 bit memory array bank3 8192 row 4096 column 2 bit input buffer output buffer a0 to a12, ba0, ba1 a0 to a12, ba0, ba1 a0 to a9, a11, a12
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 9 pin functions clk (input pin): clk is the master clock input to this pin. the other input signals are referred at clk rising edge. cs (input pin): when cs is low, the command input cycle becomes valid. when cs is high, all inputs are ignored. however, internal operations (bank active, burst operations, etc.) are held. ras , cas , and we (input pins): although these pin names are the same as those of conventional drams, they function in a different way. these pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. for details, refer to the command operation section. a0 to a12 (input pins): row address (ax0 to ax12) is determined by a0 to a12 level at the bank active command cycle clk rising edge. column address (ay0 to ay9; hm5259165b, ay0 to ay9, ay11; hm5259805b, ay0 to ay9, ay11, ay12; hm5259405b) is determined by a0 to a8, a9 a11 or a12 (a9; hm5259165b, a9, a11; hm5259805b, a9, a11, a12; hm5259405b) level at the read or write command cycle clk rising edge. and this column address becomes burst access start address. a10 defines the precharge mode. when a10 = high at the precharge command cycle, all banks are precharged. but when a10 = low at the precharge command cycle, only the bank that is selected by ba0/ba1 (bs) is precharged. for details refer to the command operation section. ba0/ba1 (input pin): ba0/ba1 are bank select signal (bs). the memory array of the hm 5259165b, hm5259805b, the hm5259405b is divided into bank 0, bank 1, bank 2 and bank 3. hm5259165b contain 8192-row 1024-column 16-bit. hm5259805b contain 8192-row 2048-column 8-bit. hm5259405b contain 8192-row 4096-column 4-bit. if ba0 is low and ba1 is low, bank 0 is selected. if ba0 is low and ba1 is high, bank 1 is selected. if ba0 is high and ba1 is low, bank 2 is selected. if ba0 is high and ba1 is high, bank 3 is selected. cke (input pin): this pin determines whether or not the next clk is valid. if cke is high, the next clk rising edge is valid. if cke is low, the next clk rising edge is invalid. this pin is used for power-down mode, clock suspend mode and self refresh mode. dqm, dqmu/dqml (input pins): dqm, dqmu/dqml controls input/output buffers. read operation: if dqm, dqmu/dqml is high, the output buffer becomes high-z. if the dqm, dqmu/dqml is low, the output buffer becomes low-z. (the latency of dqm, dqmu/dqml during reading is 2 clocks.) write operation: if dqm, dqmu/dqml is high, the previous data is held (the new data is not written). if dqm, dqmu/dqml is low, the data is written. (the latency of dqm, dqmu/dqml during writing is 0 clock.) dq0 to dq15 (dq pins): data is input to and output from these pins (dq0 to dq15; hm5259165b, dq0 to dq7; hm5259805b, dq0 to dq3; hm5259405b). v cc and v cc q (power supply pins): 3.3 v is applied. (v cc is for the internal circuit and v cc q is for the output buffer.)
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 10 v ss and v ss q (power supply pins): ground is connected. (v ss is for the internal circuit and v ss q is for the output buffer.) command operation command truth table the sdram recognizes the following commands specified by the cs , ras , cas , we and address pins. cke command symbol n - 1 n cs ras cas we ba0/ba1 a10 a0 to a12 ignore command desl h h no operation nop h lh h h column address and read command read h lh l hv l v read with auto-precharge read a h lh l hv h v column address and write command writ h lh l l v l v write with auto-precharge writ a h lh l l v h v row address strobe and bank active actv h ll h hv v v precharge select bank pre h ll h l v l precharge all bank pall h ll h l h refresh ref/self h v l l l h mode register set mrs h ll l l v v v note: h: v ih . l: v il . : v ih or v il . v: valid address input ignore command [desl]: when this command is set ( cs is high), the sdram ignore command input at the clock. however, the internal status is held. no operation [nop]: this command is not an execution command. however, the internal operations continue. column address strobe and read command [read]: this command starts a read operation. in addition, the start address of burst read is determined by the column address (ay0 to ay9; hm5259165b, ay0 to ay9, ay11; hm5259805b, ay0 to ay9, ay11, ay12; hm5259405b) and the bank select address (bs). after the read operation, the output buffer becomes high-z. read with auto-precharge [read a]: this command automatically performs a precharge operation after a burst read with a burst length of 1, 2, 4 or 8.
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 11 column address strobe and write command [writ]: this command starts a write operation. when the burst write mode is selected, the column address (ay0 to ay9; hm5259165b, ay0 to ay9, ay11; hm5259805b, ay0 to ay9, ay11, ay12; hm5259405b) and the bank select address (ba0/ba1) become the burst write start address. when the single write mode is selected, data is only written to the location specified by the column address (ay0 to ay9; hm5259165b, ay0 to ay9, ay11; hm5259805b, ay0 to ay9, ay11, ay12; hm5259405b) and the bank select address (ba0/ba1). write with auto-precharge [writ a]: this command automatically performs a precharge operation after a burst write with a length of 1, 2, 4 or 8, or after a single write operation. row address strobe and bank activate [actv]: this command activates the bank that is selected by ba0/ba1 (bs) and determines the row address (ax0 to ax12). when ba0 and ba1 are low, bank 0 is activated. when ba0 is low and ba1 is high, bank 1 is activated. when ba0 is high and ba1 is low, bank 2 is activated. when ba0 and ba1 are high, bank 3 is activated. precharge selected bank [pre]: this command starts precharge operation for the bank selected by ba0/ba1. if ba0 and ba1 are low, bank 0 is selected. if ba0 is low and ba1 is high, bank 1 is selected. if ba0 is high and ba1 is low, bank 2 is selected. if ba0 and ba1 are high, bank 3 is selected. precharge all banks [pall]: this command starts a precharge operation for all banks. refresh [ref/self]: this command starts the refresh operation. there are two types of refresh operation, the one is auto-refresh, and the other is self-refresh. for details, refer to the cke truth table section. mode register set [mrs]: the sdram has a mode register that defines how it operates. the mode register is specified by the address pins (a0 to ba0 and ba1) at the mode register set cycle. for details, refer to the mode register configuration. after power on, the contents of the mode register are undefined, execute the mode register set command to set up the mode register.
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 12 dqm truth table (hm5259165b) cke command symbol n - 1 n dqmu dqml upper byte (dq8 to dq15) write enable/output enable enbu h l lower byte (dq0 to dq7) write enable/output enable enbl h l upper byte (dq8 to dq15) write inhibit/output disable masku h h lower byte (dq0 to dq7) write inhibit/output disable maskl h h note: h: v ih . l: v il . : v ih or v il . write: i did is needed. read: i dod is needed. dqm truth table (hm5259805b/hm5259405b) cke command symbol n - 1 n dqm write enable/output enable enb h l write inhibit/output disable mask h h note: h: v ih . l: v il . : v ih or v il . write: i did is needed. read: i dod is needed. the sdram can mask input/output data by means of dqm, dqmu/dqml. dqmu masks the upper byte and dqml masks the lower byte. (hm5259165b) during reading, the output buffer is set to low-z by setting dqm, dqmu/dqml to low, enabling data output. on the other hand, when dqm, dqmu/dqml is set to high, the output buffer becomes high-z, disabling data output. during writing, data is written by setting dqm, dqmu/dqml to low. when dqm, dqmu/dqml is set to high, the previous data is held (the new data is not written). desired data can be masked during burst read or burst write by setting dqmu/dqml. for details, refer to the dqm, dqmu/dqml control section of the sdram operating instructions.
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 13 cke truth table cke current state command n - 1 n cs ras cas we address active clock suspend mode entry h l any clock suspend l l clock suspend clock suspend mode exit l h idle auto-refresh command (ref) h h lllh idle self-refresh entry (self) h llllh idle power down entry h l l h h h hl h self refresh self refresh exit (selfx) l h l h h h lhh power down power down exit l h l h h h lhh note: h: v ih . l: v il . : v ih or v il . clock suspend mode entry: the sdram enters clock suspend mode from active mode by setting cke to low. if command is input in the clock suspend mode entry cycle, the command is valid. the clock suspend mode changes depending on the current status (1 clock before) as shown below. active clock suspend: this suspend mode ignores inputs after the next clock by internally maintaining the bank active status. read suspend and read with auto-precharge suspend: the data being output is held (and continues to be output). write suspend and writ with auto-precharge suspend: in this mode, external signals are not accepted. however, the internal state is held. clock suspend: during clock suspend mode, keep the cke to low. clock suspend mode exit: the sdram exits from clock suspend mode by setting cke to high during the clock suspend state. idle: in this state, all banks are not selected, and completed precharge operation. auto-refresh command [ref]: when this command is input from the idle state, the sdram starts auto- refresh operation. (the auto-refresh is the same as the cbr refresh of conventional drams.) during the auto-refresh operation, refresh address and bank select address are generated inside the sdram. for every auto-refresh cycle, the internal address counter is updated. accordingly, 8192 times are required to refresh the entire memory. before executing the auto-refresh command, all the banks must be in the idle state. in addition, since the precharge for all banks is automatically performed after auto-refresh, no precharge command is required after auto-refresh.
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 14 self-refresh entry [self]: when this command is input during the idle state, the sdram starts self- refresh operation. after the execution of this command, self-refresh continues while cke is low. since self- refresh is performed internally and automatically, external refresh operations are unnecessary. power down mode entry: when this command is executed during the idle state, the sdram enters power down mode. in power down mode, power consumption is suppressed by cutting off the initial input circuit. self-refresh exit: when this command is executed during self-refresh mode, the sdram can exit from self- refresh mode. after exiting from self-refresh mode, the sdram enters the idle state. power down exit: when this command is executed at the power down mode, the sdram can exit from power down mode. after exiting from power down mode, the sdram enters the idle state. function truth table the following table shows the operations that are performed when each command is issued in each mode of the sdram. the following table assumes that cke is high. current state cs ras cas we address command operation precharge h desl enter idle after t rp lhhh nop enter idle after t rp l h l h ba, ca, a10 read/read a illegal* 4 l h l l ba, ca, a10 writ/writ a illegal* 4 l l h h ba, ra actv illegal* 4 l l h l ba, a10 pre, pall nop* 6 ll lh ref, self illegal l l l l mode mrs illegal idle h desl nop lhhh nop nop l h l h ba, ca, a10 read/read a illegal* 5 l h l l ba, ca, a10 writ/writ a illegal* 5 l l h h ba, ra actv bank and row active l l h l ba, a10 pre, pall nop ll lh ref, self refresh l l l l mode mrs mode register set
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 15 current state cs ras cas we address command operation row active h desl nop lhhh nop nop l h l h ba, ca, a10 read/read a begin read l h l l ba, ca, a10 writ/writ a begin write l l h h ba, ra actv other bank active illegal on same bank* 3 l l h l ba, a10 pre, pall precharge ll lh ref, self illegal l l l l mode mrs illegal read h desl continue burst to end lhhh nop continue burst to end l h l h ba, ca, a10 read/read a continue burst read to cas latency and new read l h l l ba, ca, a10 writ/writ a term burst read/start write l l h h ba, ra actv other bank active illegal on same bank* 3 l l h l ba, a10 pre, pall term burst read and precharge ll lh ref, self illegal l l l l mode mrs illegal read with auto- precharge h desl continue burst to end and precharge lhhh nop continue burst to end and precharge l h l h ba, ca, a10 read/read a illegal* 4 l h l l ba, ca, a10 writ/writ a illegal* 4 l l h h ba, ra actv other bank active illegal on same bank* 3 l l h l ba, a10 pre, pall illegal* 4 ll lh ref, self illegal l l l l mode mrs illegal
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 16 current state cs ras cas we address command operation write h desl continue burst to end lhhh nop continue burst to end l h l h ba, ca, a10 read/read a term burst and new read l h l l ba, ca, a10 writ/writ a term burst and new write l l h h ba, ra actv other bank active illegal on same bank* 3 l l h l ba, a10 pre, pall term burst write and precharge* 2 ll lh ref, self illegal l l l l mode mrs illegal write with auto- precharge h desl continue burst to end and precharge lhhh nop continue burst to end and precharge l h l h ba, ca, a10 read/read a illegal* 4 l h l l ba, ca, a10 writ/writ a illegal* 4 l l h h ba, ra actv other bank active illegal on same bank* 3 l l h l ba, a10 pre, pall illegal* 4 ll lh ref, self illegal l l l l mode mrs illegal refresh (auto- refresh) h desl enter idle after t rc lhhh nop enter idle after t rc l h l h ba, ca, a10 read/read a illegal* 5 l h l l ba, ca, a10 writ/writ a illegal* 5 l l h h ba, ra actv illegal* 5 l l h l ba, a10 pre, pall illegal* 5 ll lh ref, self illegal l l l l mode mrs illegal notes: 1. h: v ih . l: v il . : v ih or v il . the other combinations are inhibit. 2. an interval of t dpl is required between the final valid data input and the precharge command. 3. if t rrd is not satisfied, this operation is illegal. 4. illegal for same bank, except for another bank. 5. illegal for all banks. 6. nop for same bank, except for another bank.
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 17 from precharge state, command operation to [desl], [nop]: when these commands are executed, the sdram enters the idle state after t rp has elapsed from the completion of precharge. from idle state, command operation to [desl], [nop], [pre] or [pall]: these commands result in no operation. to [actv]: the bank specified by the address pins and the row address is activated. to [ref], [self]: the sdram enters refresh mode (auto-refresh or self-refresh). to [mrs]: the synchronous dram enters the mode register set cycle. from row active state, command operation to [desl], [nop]: these commands result in no operation. to [read], [read a]: a read operation starts. (however, an interval of t rcd is required.) to [writ], [writ a]: a write operation starts. (however, an interval of t rcd is required.) to [actv]: this command makes the other bank active. (however, an interval of t rrd is required.) attempting to make the currently active bank active results in an illegal command. to [pre], [pall]: these commands set the sdram to precharge mode. (however, an interval of t ras is required.) from read state, command operation to [desl], [nop]: these commands continue read operations until the burst operation is completed. to [read], [read a]: data output by the previous read command continues to be output. after cas latency, the data output resulting from the next command will start. to [writ], [writ a]: these commands stop a burst read, and start a write cycle. to [actv]: this command makes other banks bank active. (however, an interval of t rrd is required.) attempting to make the currently active bank active results in an illegal command. to [pre], [pall]: these commands stop a burst read, and the sdram enters precharge mode.
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 18 from read with auto-precharge state, command operation to [desl], [nop]: these commands continue read operations until the burst operation is completed, and the sdram then enters precharge mode. to [actv]: this command makes other banks bank active. (however, an interval of t rrd is required.) attempting to make the currently active bank active results in an illegal command. from write state, command operation to [desl], [nop]: these commands continue write operations until the burst operation is completed. to [read], [read a]: these commands stop a burst and start a read cycle. to [writ], [writ a]: these commands stop a burst and start the next write cycle. to [actv]: this command makes the other bank active. (however, an interval of t rrd is required.) attempting to make the currently active bank active results in an illegal command. to [pre], [pall]: these commands stop burst write and the sdram then enters precharge mode. from write with auto-precharge state, command operation to [desl], [nop]: these commands continue write operations until the burst is completed, and the synchronous dram enters precharge mode. to [actv]: this command makes the other bank active. (however, an interval of t rrd is required.) attempting to make the currently active bank active results in an illegal command. from refresh state, command operation to [desl], [nop]: after an auto-refresh cycle (after t rc ), the sdram automatically enters the idle state.
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 19 simplified state diagram precharge write suspend read suspend row active idle idle power down auto refresh self refresh mode register set power on writea writea suspend reada reada suspend active clock suspend sr entry sr exit mrs refresh cke cke_ active write read write with ap read with ap power applied cke cke_ cke cke_ cke cke_ cke cke_ cke cke_ precharge ap read write write with ap read with read with ap write with ap precharge precharge precharge *1 read read write write automatic transition after completion of command. transition resulting from command input. note: 1. after the auto-refresh operation, precharge operation is performed automatically and enter the idle state.
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 20 mode register configuration the mode register is set by the input to the address pins (a0 to a12, ba0 and ba1) during mode register set cycles. the mode register consists of five sections, each of which is assigned to address pins. ba1, ba0, a11, a10, a12, a9, a8: (opcode): the sdram has two types of write modes. one is the burst write mode, and the other is the single write mode. these bits specify write mode. burst read and burst write: burst write is performed for the specified burst length starting from the column address specified in the write cycle. burst read and single write: data is only written to the column address specified during the write cycle, regardless of the burst length. a7: keep this bit low at the mode register set cycle. if this pin is high, the vender test mode is set. a6, a5, a4: (lmode): these pins specify the cas latency. a3: (bt): a burst type is specified. a2, a1, a0: (bl): these pins specify the burst length. a2 a1 a0 burst length 00 0 1 00 1 2 01 0 4 01 1 8 11 1 bt=0 bt=1 10 0 r 11 0 r r 1 2 4 8 r r r a3 0 sequential 1 interleave burst type a6 a5 a4 cas latency 00 0 r 00 1 r 01 0 2 01 1 3 1xx r a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 opcode 0 lmode bt bl a9 0 0r write mode a8 0 1 burst read and burst write 1 burst read and single write 0 1r 1 10 1 r r r is reserved (inhibit) x: 0 or 1 a11 a10 a10 x x x a11 x x x 00 a12 ba0 ba1 ba1 ba0 x x x 0 x x x 0 a12 x x x 0
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 21 burst sequence a2 a1 a0 addressing(decimal) 00 0 00 1 01 0 01 1 11 1 interleave sequential 10 0 11 0 10 1 starting ad. 0, 1, 2, 3, 4, 5, 6, 7, 1, 2, 3, 4, 5, 6, 7, 2, 3, 4, 5, 6, 7, 3, 4, 5, 6, 7, 4, 5, 6, 7, 5, 6, 7, 6, 7, 7, 0, 0, 1, 0, 1, 2, 0, 1, 2, 3, 0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 6, 0, 1, 2, 3, 4, 5, 6, 7, 1, 0, 3, 2, 5, 4, 7, 2, 3, 0, 1, 6, 7, 3, 2, 1, 0, 7, 4, 5, 6, 7, 5, 4, 7, 6, 7, 7, 6, 4, 5, 6, 5, 4, 0, 1, 2, 3, 6, 1, 0, 3, 2, 4, 5, 2, 3, 0, 1, 6, 5, 4, 3, 2, 1, 0, burst length = 8 a1 a0 addressing(decimal) 00 01 10 11 interleave sequential starting ad. 0, 1, 2, 3, 1, 2, 3, 0, 2, 3, 0, 1, 3, 0, 1, 2, 0, 1, 2, 3, 1, 0, 3, 2, 2, 3, 0, 1, 3, 2, 1, 0, burst length = 4 a0 addressing(decimal) 0 1 interleave sequential starting ad. 0, 1, 1, 0, 0, 1, 1, 0, burst length = 2
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 22 operation of the sdram the following chapter shows operation example of the products below. organization input/output mask cas latency 8-mword 16-bit 4 bank dqmu/dqml 2/3 16-mword 8-bit 4 bank dqm 32-mword 4-bit 4 bank dqm note: the sdram should be used according to the product capability (see ?eatures? ?in description and ?c characteristics?. read/write operations bank active: before executing a read or write operation, the corresponding bank and the row address must be activated by the bank active (actv) command. an interval of t rcd is required between the bank active command input and the following read/write command input. read operation: a read operation starts when a read command is input. output buffer becomes low-z in the ( cas latency - 1) cycle after read command set. the sdram can perform a burst read operation. the burst length can be set to 1, 2, 4, 8. the start address for a burst read is specified by the column address and the bank select address (ba0/ba1) at the read command set cycle. in a read operation, data output starts after the number of clocks specified by the cas latency. the cas latency can be set to 2 or 3. when the burst length is 1, 2, 4, 8, the dout buffer automatically becomes high-z at the next clock after the successive burst-length data has been output. the cas latency and burst length must be specified at the mode register.
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 23 cas latency read clk command dout actv row column address cl = 2 cl = 3 out 0 out 1 out 2 out 3 out 0 out 1 out 2 out 3 t rcd cl = cas latency burst length = 4 burst length read clk command dout actv row column out 0 out 6 out 7 address out 0 out 1 out 4 out 5 out 0 out 1 out 2 out 3 bl = 1 out 0 out 1 out 2 out 3 bl = 2 bl = 4 bl = 8 t rcd bl : burst length cas latency = 2
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 24 write operation: burst write or single write mode is selected by the opcode (ba1, ba0, a12, a11, a10, a9, a8) of the mode register. 1. burst write: a burst write operation is enabled by setting opcode (a9, a8) to (0, 0). a burst write starts in the same clock as a write command set. (the latency of data input is 0 clock.) the burst length can be set to 1, 2, 4 and 8, like burst read operations. the write start address is specified by the column address and the bank select address (ba0/ba1) at the write command set cycle. writ clk command din actv row column in 0 in 6 in 7 address in 1 in 4 in 5 in 3 bl = 1 bl = 2 bl = 4 bl = 8 t rcd in 0 in 0 in 0 in 1 in 1 in 2 in 2 in 3 cas latency = 2, 3 2. single write: a single write operation is enabled by setting opcode (a9, a8) to (1, 0). in a single write operation, data is only written to the column address and the bank select address (ba0/ba1) specified by the write command set cycle without regard to the burst length setting. (the latency of data input is 0 clock). writ clk command din actv row column in 0 address t rcd
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 25 auto precharge read with auto-precharge: in this operation, since precharge is automatically performed after completing a read operation, a precharge command need not be executed after each read operation. the command executed for the same bank after the execution of this command must be the bank active (actv) command. in addition, an interval defined by l apr is required before execution of the next command. cas latency precharge start cycle 3 2 cycle before the final data is output 2 1 cycle before the final data is output burst read (burst length = 4) clk l apr l ras l apr cl=2 command cl=3 command dq (input) dq (input) note: internal auto-precharge starts at the timing indicated by " ". and an interval of t ras (l ras ) is required between previous active (actv) command and internal precharge " ". actv read a actv out3 out2 out1 out0 l ras actv read a actv out3 out2 out1 out0
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 26 write with auto-precharge: in this operation, since precharge is automatically performed after completing a burst write or single write operation, a precharge command need not be executed after each write operation. the command executed for the same bank after the execution of this command must be the bank active (actv) command. in addition, an interval of l apw is required between the final valid data input and input of next command. burst write (burst length = 4) clk command dq (input) l apw i ras actv writ a in0 in1 in2 in3 actv note: internal auto-precharge starts at the timing indicated by " ". and an interval of t ras (l ras ) is required between previous active (actv) command and internal precharge " ". single write clk command dq (input) l apw i ras actv writ a in actv note: internal auto-precharge starts at the timing indicated by " ". and an interval of t ras (l ras ) is required between previous active (actv) command and internal precharge " ".
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 27 command intervals read command to read command interval: 1. same bank, same row address: when another read command is executed at the same row address of the same bank as the preceding read command execution, the second read can be performed after an interval of no less than 1 clock. even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. read to read command interval (same row address in same bank) clk command dout out b3 address out b1 out b2 bs actv row column a read read column b out a0 out b0 bank0 active column =a read column =b read column =a dout column =b dout cas latency = 3 burst length = 4 bank 0 2. same bank, different row address: when the row address changes on same bank, consecutive read commands cannot be executed; it is necessary to separate the two read commands with a precharge command and a bank-active command. 3. different bank: when the bank changes, the second read can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank-active state. even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. read to read command interval (different bank) clk command dout out b3 address out b1 out b2 bs actv row 0 row 1 actv read column a out a0 out b0 bank0 active bank3 active bank0 read bank3 read read column b bank0 dout bank3 dout cas latency = 3 burst length = 4
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 28 write command to write command interval: 1. same bank, same row address: when another write command is executed at the same row address of the same bank as the preceding write command, the second write can be performed after an interval of no less than 1 clock. in the case of burst writes, the second write command has priority. write to write command interval (same row address in same bank) clk command din in b3 address in b1 in b2 bs actv row column a writ writ column b in a0 in b0 bank0 active column =a write column =b write burst write mode burst length = 4 bank 0 2. same bank, different row address: when the row address changes, consecutive write commands cannot be executed; it is necessary to separate the two write commands with a precharge command and a bank-active command. 3. different bank: when the bank changes, the second write can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank-active state. in the case of burst write, the second write command has priority. write to write command interval (different bank) clk command din in b3 address in b1 in b2 bs actv row 0 row 1 actv writ column a in a0 in b0 bank0 active bank3 active bank0 write bank3 write writ column b burst write mode burst length = 4
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 29 read command to write command interval: 1. same bank, same row address: when the write command is executed at the same row address of the same bank as the preceding read command, the write command can be performed after an interval of no less than 1 clock. however, dqm, dqmu/dqml must be set high so that the output buffer becomes high-z before data input. read to write command interval (1) clk command dout in b2 in b3 read writ in b0 in b1 high-z din cl=2 cl=3 dqm, dqmu /dqml burst length = 4 burst write read to write command interval (2) clk command dout read writ din cl=2 cl=3 dqm, dqmu/dqml high-z 2 clock high-z 2. same bank, different row address: when the row address changes, consecutive write commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank- active command. 3. different bank: when the bank changes, the write command can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. however, dqm, dqmu/dqml must be set high so that the output buffer becomes high-z before data input.
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 30 write command to read command interval: 1. same bank, same row address: when the read command is executed at the same row address of the same bank as the preceding write command, the read command can be performed after an interval of no less than 1 clock. however, in the case of a burst write, data will continue to be written until one clock before the read command is executed. write to read command interval (1) clk command din writ read in a0 out b1 out b2 out b3 out b0 dout column = a write column = b read column = b dout cas latency dqm, dqmu/dqml burst write mode cas latency = 2 burst length = 4 bank 0 write to read command interval (2) clk command din writ read in a0 out b1 out b2 out b3 out b0 dout column = a write column = b read column = b dout cas latency in a1 dqm, dqmu/dqml burst write mode cas latency = 2 burst length = 4 bank 0 2. same bank, different row address: when the row address changes, consecutive read commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank- active command. 3. different bank: when the bank changes, the read command can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank-active state. however, in the case of a burst write, data will continue to be written until one clock before the read command is executed (as in the case of the same bank and the same address).
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 31 read with auto precharge to read command interval 1. different bank: when some banks are in the active state, the second read command (another bank) is executed. even when the first read with auto-precharge is a burst read that is not yet finished, the data read by the second command is valid. the internal auto-precharge of one bank starts at the next clock of the second command. read with auto precharge to read command interval (different bank) clk command bs dout read a read out a0 out a1 out b0 out b1 cas latency = 3 burst length = 4 bank0 read a bank3 read note: internal auto-precharge starts at the timing indicated by " ". 2. same bank: the consecutive read command (the same bank) is illegal. write with auto precharge to write command interval 1. different bank: when some banks are in the active state, the second write command (another bank) is executed. in the case of burst writes, the second write command has priority. the internal auto-precharge of one bank starts at the next clock of the second command . write with auto precharge to write command interval (different bank) clk command bs din writ a writ in b1 in b2 in b3 in a0 in a1 in b0 burst length = 4 bank0 write a bank3 write note: internal auto-precharge starts at the timing indicated by " ". 2. same bank: the consecutive write command (the same bank) is illegal.
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 32 read with auto precharge to write command interval 1. different bank: when some banks are in the active state, the second write command (another bank) is executed. however, dqm, dqmu/dqml must be set high so that the output buffer becomes high-z before data input. the internal auto-precharge of one bank starts at the next clock of the second command. read with auto precharge to write command interval (different bank) clk command bs dout din cl = 2 cl = 3 read a writ in b0 in b1 in b2 in b3 burst length = 4 bank0 read a bank3 write note: internal auto-precharge starts at the timing indicated by " ". dqm, dqmu/dqml high-z 2. same bank: the consecutive write command from read with auto precharge (the same bank) is illegal. it is necessary to separate the two commands with a bank active command.
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 33 write with auto precharge to read command interval 1. different bank: when some banks are in the active state, the second read command (another bank) is executed. however,in case of a burst write, data will continue to be written until one clock before the read command is executed. the internal auto-precharge of one bank starts at the next clock of the second command. write with auto precharge to read command interval (different bank) clk command bs dout din writ a read out b0 out b1 out b2 out b3 cas latency = 3 burst length = 4 bank0 write a bank3 read note: internal auto-precharge starts at the timing indicated by " ". dqm, dqmu/dqml in a0 2. same bank: the consecutive read command from write with auto precharge (the same bank) is illegal. it is necessary to separate the two commands with a bank active command.
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 34 read command to precharge command interval (same bank): when the precharge command is executed for the same bank as the read command that preceded it, the minimum interval between the two commands is one clock. however, since the output buffer then becomes high-z after the clocks defined by l hzp , there is a case of interruption to burst read data output will be interrupted, if the precharge command is input during burst read. to read all data by burst read, the clocks defined by l ep must be assured as an interval from the final data output to precharge command execution. read to precharge command interval (same bank): to output all data cas latency = 2, burst length = 4 clk command dout read pre/pall out a0 out a1 out a2 out a3 cl=2 l = -1 cycle ep cas latency = 3, burst length = 4 clk command dout read pre/pall out a0 out a1 out a2 out a3 cl=3 l = -2 cycle ep
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 35 read to precharge command interval (same bank): to stop output data cas latency = 2, burst length = 1, 2, 4, 8 clk command dout read pre/pall out a0 l hzp =2 high-z cas latency = 3, burst length = 1, 2, 4, 8 clk command dout read pre/pall out a0 l hzp =3 high-z
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 36 write command to precharge command interval (same bank): when the precharge command is executed for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 clock. however, if the burst write operation is unfinished, the input data must be masked by means of dqm, dqmu/dqml for assurance of the clock defined by t dpl . write to precharge command interval (same bank) burst length = 4 (to stop write operation) clk command din writ pre/pall t dpl dqm, dqmu/dqml clk in a0 in a1 command din writ pre/pall dqm, dqmu/dqml t dpl burst length = 4 (to write all data) clk in a0 in a1 in a2 command din writ pre/pall in a3 dqm, dqmu/dqml t dpl
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 37 bank active command interval: 1. same bank: the interval between the two bank-active commands must be no less than t rc . 2. in the case of different bank-active commands: the interval between the two bank-active commands must be no less than t rrd . bank active to bank active for same bank clk command address bs bank 0 active actv row actv row bank 0 active t rc bank active to bank active for different bank clk command address bs bank 0 active bank 3 active actv row:0 actv row:1 t rrd
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 38 mode register set to bank-active command interval: the interval between setting the mode register and executing a bank-active command must be no less than l rsa . clk command address mode register set bank active mrs actv i rsa bs & row code
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 39 dqm control the dqm mask the dq data. the dqmu and dqml mask the upper and lower bytes of the dq data, respectively. the timing of dqmu/dqml is different during reading and writing. reading: when data is read, the output buffer can be controlled by dqm, dqmu/dqml. by setting dqm, dqmu/dqml to low, the output buffer becomes low-z, enabling data output. by setting dqm, dqmu/dqml to high, the output buffer becomes high-z, and the corresponding data is not output. however, internal reading operations continue. the latency of dqm, dqmu/dqml during reading is 2 clocks. writing: input data can be masked by dqm, dqmu/dqml. by setting dqm, dqmu/dqml to low, data can be written. in addition, when dqm, dqmu/dqml is set to high, the corresponding data is not written, and the previous data is held. the latency of dqm, dqmu/dqml during writing is 0 clock. reading clk dq (output) out 0 out 1 l = 2 latency out 3 dod dqm, dqmu/dqml high-z writing clk dq (input) in 0 in 1 l = 0 latency in 3 did dqm, dqmu/dqml
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 40 refresh auto-refresh: all the banks must be precharged before executing an auto-refresh command. since the auto- refresh command updates the internal counter every time it is executed and determines the banks and the row addresses to be refreshed, external address specification is not required. the refresh cycle is 8192 cycles/32 ms. (8192 cycles are required to refresh all the row addresses.) the output buffer becomes high- z after auto-refresh start. in addition, since a precharge has been completed by an internal operation after the auto-refresh, an additional precharge operation by the precharge command is not required. self-refresh: after executing a self-refresh command, the self-refresh operation continues while cke is held low. during self-refresh operation, all row addresses are refreshed by the internal refresh timer. a self- refresh is terminated by a self-refresh exit command. before and after self-refresh mode, execute auto-refresh to all refresh addresses in or within 32 ms period on the condition (1) and (2) below. (1) enter self-refresh mode within 3.9 s after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. (2) start burst refresh or distributed refresh at equal interval to all refresh addresses within 3.9 s after exiting from self-refresh mode. others power-down mode: the sdram enters power-down mode when cke goes low in the idle state. in power down mode, power consumption is suppressed by deactivating the input initial circuit. power down mode continues while cke is held low. in addition, by setting cke to high, the sdram exits from the power down mode, and command input is enabled from the next clock. in this mode, internal refresh is not performed. clock suspend mode: by driving cke to low during a bank-active or read/write operation, the sdram enters clock suspend mode. during clock suspend mode, external input signals are ignored and the internal state is maintained. when cke is driven high, the sdram terminates clock suspend mode, and command input is enabled from the next clock. for details, refer to the "cke truth table". power-up sequence: the sdram should be goes on the following sequence with power up. the clk, cke, cs , dqm, dqmu/dqml and dq pins keep low till power stabilizes. the clk pin is stabilized within 100 s after power stabilizes before the following initialization sequence. the cke and dqm, dqmu/dqml is driven to high between power stabilizes and the initialization sequence. this sdram has v cc clamp diodes for clk, cke, cs dqm, dqmu/dqml and dq pins. if these pins go high before power up, the large current flows from these pins to v cc through the diodes. initialization sequence: when 200 s or more has past after the above power-up sequence, all banks must be precharged using the precharge command (pall). after t rp delay, set 8 or more auto refresh commands (ref). set the mode register set command (mrs) to initialize the mode register. we recommend that by keeping dqm, dqmu/dqml and cke to high, the output buffer becomes high-z during initialization sequence, to avoid dq bus contention on memory system formed with a number of device.
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 41 v cc , v cc q power up sequence initialization sequence 100 s 0 v low low low cke, dqm, dqmu/dqml clk cs , dq 200 s power stabilize absolute maximum ratings parameter symbol value unit note voltage on any pin relative to v ss v t ?.5 to v cc + 0.5 ( 4.6 (max)) v1 supply voltage relative to v ss v cc ?.5 to +4.6 v 1 short circuit output current iout 50 ma power dissipation p t 1.2 w operating temperature topr 0 to +70 ? storage temperature tstg ?5 to +125 ? note: 1. respect to v ss . dc operating conditions (ta = 0 to +70 ? c) parameter symbol min max unit notes supply voltage v cc , v cc q 3.0 3.6 v 1, 2 v ss , v ss q0 0 v 3 input high voltage v ih 2.0 v cc + 0.3 v 1, 4 input low voltage v il 0.3 0.8 v 1, 5 notes: 1. all voltage referred to v ss . 2. the supply voltage with all v cc and v cc q pins must be on the same level. 3. the supply voltage with all v ss and v ss q pins must be on the same level. 4. v ih (max) = v cc + 2.0 v for pulse width 3 ns at v cc . 5. v il (min) = v ss 2.0 v for pulse width 3 ns at v ss .
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 42 v il /v ih clamp this sdram has v il and v ih clamp for clk, cke, cs, dqm and i/o pins. minimum v il clamp current v il (v) i (ma) 2 32 1.8 25 1.6 19 1.4 13 1.2 8 1 4 0.9 2 0.8 0.6 0.6 0 0.4 0 0.2 0 00 v il (v) i (ma) 1.5 1 0.5 5 15 10 25 20 30 0 35 2 0
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 43 minimum v ih clamp current v ih (v) i (ma) v cc + 2 10 v cc + 1.8 8 v cc + 1.6 5.5 v cc + 1.4 3.5 v cc + 1.2 1.5 v cc + 1 0.3 v cc + 0.8 0 v cc + 0.6 0 v cc + 0.4 0 v cc + 0.2 0 v cc + 0 0 v ih (v) v cc + 0 v cc + 1 v cc + 2 v cc + 0.5 v cc + 1.5 i (ma) 8 4 6 0 2 10
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 44 i ol /i oh characteristics output low current (i ol ) i ol i ol vout (v) min (ma) max (ma) 000 0.4 27 71 0.65 41 108 0.85 51 134 1 58 151 1.4 70 188 1.5 72 194 1.65 75 203 1.8 77 209 1.95 77 212 3 80 220 3.45 81 223 i ol (ma) vout (v) 250 200 150 100 50 0 00.511.522.533.5 min max
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 45 output high current (i oh ) (ta = 0 to +70 ? c, v cc , v cc q = 3.0 v to 3.45 v, v ss , v ss q = 0 v) i oh i oh vout (v) min (ma) max (ma) 3.45 3 3.3 28 30 75 2.6 21 130 2.4 34 154 2 59 197 1.8 67 227 1.65 73 248 1.5 78 270 1.4 81 285 1 89 345 0 93 503 i oh (ma) vout (v) 0 100 200 300 500 600 400 0.5 1 1.5 2 2.5 3 min max 3.5 0
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 46 dc characteristics (ta = 0 to +70 ? c, v cc , v cc q = 3.3 v 0.3 v, v ss , v ss q = 0 v) (hm5259165b) hm5259165b -75 -a6 parameter symbol min max min max unit test conditions notes operating current ( cas latency = 2) i cc1 220 190 ma burst length = 1 t rc = min 1, 2, 3 ( cas latency = 3) i cc1 220 190 ma standby current in power down i cc2p 6 6 ma cke = v il , t ck = 12 ns 6 standby current in power down (input signal stable) i cc2ps 4 4 ma cke = v il , t ck = 7 standby current in non power down i cc2n 40 40 ma cke, cs = v ih , t ck = 12 ns 4 standby current in non power down (input signal stable) i cc2ns 18 18 ma cke = v ih , t ck = 9 active standby current in power down i cc3p 8 8 ma cke = v il , t ck = 12 ns 1, 2, 6 active standby current in power down (input signal stable) i cc3ps 6 6 ma cke = v il , t ck = 2, 7 active standby current in non power down i cc3n 60 60 ma cke, cs = v ih , t ck = 12 ns 1, 2, 4 active standby current in non power down (input signal stable) i cc3ns 30 30 ma cke = v ih , t ck = 2, 9 burst operating current ( cas latency = 2) i cc4 200 200 ma t ck = min, bl = 4 1, 2, 5 ( cas latency = 3) i cc4 270 200 ma refresh current i cc5 330 330 ma t rc = min 3 self refresh current i cc6 6 6mav ih v cc 0.2 v v il 0.2 v 8 input leakage current i li 11 1 1 a 0 vin v cc output leakage current i lo 1.5 1.5 1.5 1.5 a 0 vout v cc dq = disable output high voltage v oh 2.4 2.4 vi oh = 4 ma output low voltage v ol 0.4 0.4 v i ol = 4 ma
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 47 dc characteristics (ta = 0 to +70 ? c, v cc , v cc q = 3.3 v 0.3 v, v ss , v ss q = 0 v) (hm5259805b) hm5259805b -75 -a6 parameter symbol min max min max unit test conditions notes operating current ( cas latency = 2) i cc1 220 190 ma burst length = 1 t rc = min 1, 2, 3 ( cas latency = 3) i cc1 220 190 ma standby current in power down i cc2p 6 6 ma cke = v il , t ck = 12 ns 6 standby current in power down (input signal stable) i cc2ps 4 4 ma cke = v il , t ck = 7 standby current in non power down i cc2n 40 40 ma cke, cs = v ih , t ck = 12 ns 4 standby current in non power down (input signal stable) i cc2ns 18 18 ma cke = v ih , t ck = 9 active standby current in power down i cc3p 8 8 ma cke = v il , t ck = 12 ns 1, 2, 6 active standby current in power down (input signal stable) i cc3ps 6 6 ma cke = v il , t ck = 2, 7 active standby current in non power down i cc3n 60 60 ma cke, cs = v ih , t ck = 12 ns 1, 2, 4 active standby current in non power down (input signal stable) i cc3ns 30 30 ma cke = v ih , t ck = 2, 9 burst operating current ( cas latency = 2) i cc4 190 190 ma t ck = min, bl = 4 1, 2, 5 ( cas latency = 3) i cc4 260 190 ma refresh current i cc5 330 330 ma t rc = min 3 self refresh current i cc6 6 6mav ih v cc 0.2 v v il 0.2 v 8 input leakage current i li 11 1 1 a 0 vin v cc output leakage current i lo 1.5 1.5 1.5 1.5 a 0 vout v cc dq = disable output high voltage v oh 2.4 2.4 vi oh = 4 ma output low voltage v ol 0.4 0.4 v i ol = 4 ma
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 48 dc characteristics (ta = 0 to +70 ? c, v cc , v cc q = 3.3 v 0.3 v, v ss , v ss q = 0 v) (hm5259405b) hm5259405b -75 -a6 parameter symbol min max min max unit test conditions notes operating current ( cas latency = 2) i cc1 220 190 ma burst length = 1 t rc = min 1, 2, 3 ( cas latency = 3) i cc1 220 190 ma standby current in power down i cc2p 6 6 ma cke = v il , t ck = 12 ns 6 standby current in power down (input signal stable) i cc2ps 4 4 ma cke = v il , t ck = 7 standby current in non power down i cc2n 40 40 ma cke, cs = v ih , t ck = 12 ns 4 standby current in non power down (input signal stable) i cc2ns 18 18 ma cke = v ih , t ck = 9 active standby current in power down i cc3p 8 8 ma cke = v il , t ck = 12 ns 1, 2, 6 active standby current in power down (input signal stable) i cc3ps 6 6 ma cke = v il , t ck = 2, 7 active standby current in non power down i cc3n 60 60 ma cke, cs = v ih , t ck = 12 ns 1, 2, 4 active standby current in non power down (input signal stable) i cc3ns 30 30 ma cke = v ih , t ck = 2, 9 burst operating current ( cas latency = 2) i cc4 190 190 ma t ck = min, bl = 4 1, 2, 5 ( cas latency = 3) i cc4 260 190 ma refresh current i cc5 330 330 ma t rc = min 3 self refresh current i cc6 6 6mav ih v cc 0.2 v v il 0.2 v 8 input leakage current i li 11 1 1 a 0 vin v cc output leakage current i lo 1.5 1.5 1.5 1.5 a 0 vout v cc dq = disable output high voltage v oh 2.4 2.4 vi oh = 4 ma output low voltage v ol 0.4 0.4 v i ol = 4 ma
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 49 notes: 1. i cc depends on output load condition when the device is selected. i cc (max) is specified at the output open condition. 2. one bank operation. 3. input signals are changed once per one clock. 4. input signals are changed once per two clocks. 5. input signals are changed once per four clocks. 6. after power down mode, clk operating current. 7. after power down mode, no clk operating current. 8. after self refresh mode set, self refresh current. 9. input signals are v ih or v il fixed. capacitance (ta = 25 c, v cc , v cc q = 3.3 v 0.3 v) parameter symbol min max unit notes input capacitance (clk) c i1 2.5 7 pf 1, 2, 4 input capacitance (input) c i2 2.5 7 pf 1, 2, 4 output capacitance (dq) c o 4 8 pf 1, 2, 3, 4 notes: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. measurement condition: f = 1 mhz, 1.4 v bias, 200 mv swing. 3. dqm, dqmu/dqml = v ih to disable dout. 4. this parameter is sampled and not 100% tested.
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 50 ac characteristics (ta = 0 to +70 ? c, v cc , v cc q = 3.3 v 0.3 v, v ss , v ss q = 0 v) hm5259165b/ hm5259805b/ hm5259405b -75 -a6 parameter symbol pc/100 symbol min max min max unit notes system clock cycle time ( cas latency = 2) t ck tclk 10 10 ns 1 ( cas latency = 3) t ck tclk 7.5 10 ns clk high pulse width t ckh tch 2.5 3 ns 1 clk low pulse width t ckl tcl 2.5 3 ns 1 access time from clk ( cas latency = 2) t ac tac 6 6 ns 1, 2 ( cas latency = 3) t ac tac 5.4 6ns data-out hold time t oh toh 2.7 3 ns 1, 2 clk to data-out low impedance t lz 2 2 ns 1, 2, 3 clk to data-out high impedance ( cas latency = 2, 3) t hz 5.4 6 ns 1, 4 input setup time t as , t cs , t ds , t ces tsi 1.5 2 ns 1, 5, 6 cke setup time for power down exit t cesp tpde 1.5 2 ns 1 input hold time t ah , t ch , t dh , t ceh thi 0.8 1 ns 1, 5 ref/active to ref/active command period t rc trc 67.5 70 ns 1 active to precharge command period t ras tras 45 120000 50 120000 ns 1 active command to column command (same bank) t rcd trcd 20 20 ns 1 precharge to active command period t rp trp 20 20 ns 1 write recovery or data-in to precharge lead time t dpl tdpl 15 20 ns 1 active (a) to active (b) command period t rrd trrd 15 20 ns 1 transition time (rise and fall) t t 1515ns refresh period t ref 32 32 ms
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 51 notes: 1. ac measurement assumes t t = 1 ns. reference level for timing of input signals is 1.5 v. 2. access time is measured at 1.5 v. load condition is cl = 50 pf. 3. t lz (min) defines the time at which the outputs achieves the low impedance state. 4. t hz (max) defines the time at which the outputs achieves the high impedance state. 5. t ces define cke setup time to clk rising edge except power down exit command. 6. t as /t ah : address, t cs /t ch : cs , ras , cas , we , dqm, dqmu/dqml. t ds /t dh : data-in, t ces /t ceh : cke. test conditions ? input and output timing reference levels: 1.5 v ? input waveform and output load: see following figures t t 2.4 v 0.4 v 0.8 v 2.0 v input t t i/o cl
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 52 relationship between frequency and minimum latency hm5259165b/ hm5259805b/ hm5259405b parameter -75 -a6 frequency (mhz) 133 100 t ck (ns) symbol pc/100 symbol 7.5 10 notes active command to column command (same bank) l rcd 321 active command to active command (same bank) l rc 97= [l ras + l rp ] 1 active command to precharge command (same bank) l ras 651 precharge command to active command (same bank) l rp 321 write recovery or data-in to precharge command (same bank) l dpl tdpl 2 2 1 active command to active command (different bank) l rrd 221 self refresh exit time l srex tsrx 1 1 2 last data in to active command (auto precharge, same bank) l apw tdal 5 4 = [l dpl + l rp ] self refresh exit to command input l sec 97= [l rc ] 3 precharge command to high impedance ( cas latency = 2) l hzp troh 2 2 ( cas latency = 3) l hzp troh 3 3 last data out to active command (auto precharge, same bank) l apr 11 last data out to precharge (early precharge) ( cas latency = 2) l ep 1 1 ( cas latency = 3) l ep 2 2 column command to column command l ccd tccd 1 1 write command to data in latency l wcd tdwd 0 0 dqm to data in l did tdqm 0 0 dqm to data out l dod tdqz 2 2 cke to clk disable l cle tcke 1 1 register set to active command l rsa tmrd 1 1
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 53 hm5259165b/ hm5259805b/ hm5259405b parameter -75 -a6 frequency (mhz) 133 100 t ck (ns) symbol pc/100 symbol 7.5 10 notes cs to command disable l cdd 00 power down exit to command input l pec 11 notes: 1. l rcd to l rrd are recommended value. 2. be valid [desl] or [nop] at next command of self refresh exit. 3. except [desl] and [nop]
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 54 timing waveforms read cycle bank 0 active bank 0 read bank 0 precharge clk cke cs t ras t rcd t ch t cs ras cas we bs a10 address dqm, dqmu/dqml dq (input) dq (output) t ch t cs t ckh t t ck t ac t ac ckl t ac t oh t oh t oh t oh t rp t rc cas latency = 2 burst length = 4 bank 0 access = v or v t ch t cs t ch t cs t ch t cs t ah t as t ah t as t ah t as t ch t cs t ch t cs t ch t cs t ah t as t ah t as t ch t cs t ch t cs t ch t cs t ch t cs t ch t cs t ah t as t ah t as t ah t as t ch t cs t ch t cs t ch t cs t ch t cs t ah t as t ah t as t ah t as t ac t lz v ih ih il t hz
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 55 write cycle clk cke cs t ras t rcd ras cas we bs a10 address dq (input) dq (output) t ch t cs t ckh t t ck t dh t dh ckl t dh t dh t ds t ds t ds t ds t rp t rc t dpl bank 0 write t ch t cs bank 0 active bank 0 precharge t ch t cs t ch t cs t ch t cs t ch t cs t ch t cs t ch t cs t ch t cs t ah t as t ah t as t ah t as t ah t as t ah t as t ah t as t ch t cs t ah t as t ch t cs t ch t cs t ch t cs t ah t as t ch t cs t ah t as t ch t cs t ch t cs t ch t cs t ah t as t ah t as v ih cas latency = 2 burst length = 4 bank 0 access = v or v ih il dqm, dqmu/dqml
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 56 mode register set cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 clk cke cs ras cas we bs address dqm, dqmu/dqml dq (input) dq (output) high-z b b+3 b b +1 b +2 b +3 l valid c: b rsa code l rcd l rp precharge if needed mode register set bank 3 active bank 3 read r: b c: b output mask v ih l = 3 cas latency = 3 burst length = 4 = v or v ih il rcd read cycle/write cycle 0 1 2 3 4 5 6 7 8 9 1011121314151617181920 r:a c:a r:b c:b c:b' c:b" a a+1 a+2 a+3 b b+1 b+2 b+3 b' b'+1 b" b"+1 b"+2 b"+3 cke ras cs cas we address dqm, dqmu/dqml dq (output) dq (input) clk bs r:a c:a r:b c:b c:b' c:b" a a+1 a+2 a+3 b b+1 b+2 b+3 b' b'+1 b" b"+1 b"+2 b"+3 bank 0 active bank 0 read bank 3 active bank 3 read bank 3 read bank 3 read bank 0 precharge bank 3 precharge bank 0 active bank 0 write bank 3 active bank 3 write bank 3 write bank 3 write bank 0 precharge bank 3 precharge cke ras cs cas we address dqm, dqmu/dqml dq (input) dq (output) bs high-z high-z v ih v ih read cycle ras - cas delay = 3 cas latency = 3 burst length = 4 = v or v ih il write cycle ras - cas delay = 3 cas latency = 3 burst length = 4 = v or v ih il
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 57 read/single write cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 r:a c:a r:b c:a' r:a c:a c:a a a a a bank 0 active bank 0 read bank 3 active bank 0 write bank 0 precharge bank 3 precharge bank 0 active bank 0 read bank 0 write bank 0 precharge r:b bank 3 active c:a bank 0 read a a+1 a+2 a+3 bank 0 write bank 0 write cke ras cs cas we address dqm, dqmu/dqml dq (input) dq (output) clk bs cke ras cs cas we address dqm, dqmu/dqml bs c:b bc a+1 a+3 a+1 a+2 a+3 c:c v ih v ih read/single write ras - cas delay = 3 cas latency = 3 burst length = 4 = v or v ih il dq (input) dq (output)
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 58 read/burst write cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 r:a c:a r:b c:a' r:a c:a c:a a a+1 a+2 a+3 a+1 a a+1 a+2 a+3 bank 0 active bank 0 read bank 0 write bank 0 precharge r:b bank 3 active cke ras cs cas we address dqm, dqmu/dqml clk bs cke ras cs cas we address dqm, dqmu/dqml bs a+1 a+2 a+3 a a+3 a bank 0 active bank 0 read bank 3 active clock suspend bank 0 write bank 0 precharge bank 3 precharge v ih read/burst write ras - cas delay = 3 cas latency = 3 burst length = 4 = v or v ih il dq (input) dq (output) dq (input) dq (output)
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 59 auto refresh cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 clk cke cs cas we bs address dqm, dqmu/dqml dq (input) dq (output) high-z rp precharge if needed auto refresh active bank 0 t rc t rc t auto refresh read bank 0 r:a c:a a10=1 ras a a+1 v ih refresh cycle and read cycle ras - cas delay = 2 cas latency = 2 burst length = 4 = v or v ih il self refresh cycle clk cke cs ras cas we bs address dqm, dqmu/dqml dq (input) dq (output) precharge command if needed self refresh entry command auto refresh self refresh exit ignore command or no operation cke low a10=1 rc t rp t self refresh cycle ras - cas delay = 3 cas latency = 3 burst length = 4 = v or v ih il high-z next clock enable rc t next clock enable l srex self refresh entry command
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 60 clock suspend mode 0123 4 5 6 7 8 9 1011121314151617181920 r:a c:a r:b a a+1 a+2 a+3 b b+1 b+2 r:a c:a r:b c:b a a+1 a+2 b b+1 b+2 b+3 c:b bank0 active active clock suspend start active clock supend end bank0 read bank3 active read suspend start read suspend end bank0 precharge bank3 read earliest bank3 precharge bank0 write bank0 active active clock suspend start active clock suspend end bank3 active write suspend start write suspend end bank3 write bank0 precharge earliest bank3 precharge b+3 cke ras cs cas we address dqm, dqmu/dqml clk bs cke ras cs cas we address dqm, dqmu/dqml bs a+3 high-z high-z t ces t ceh t ces read cycle ras - cas delay = 2 cas latency = 2 burst length = 4 = v or v ih il write cycle ras - cas delay = 2 cas latency = 2 burst length = 4 = v or v ih il dq (output) dq (input) dq (output) dq (input)
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 61 power down mode clk cke cs ras cas we bs address dqm, dqmu/dqml dq (input) dq (output) precharge command if needed power down entry active bank 0 power down mode exit cke low r: a a10=1 rp t high-z power down cycle ras - cas delay = 3 cas latency = 3 burst length = 4 = v or v ih il initialization sequence 78910 52 53 54 48 49 50 51 auto refresh bank active if needed rc t rc t auto refresh valid 0 123456 clk cke cs ras cas we address dqm, dqmu/dqml dq t valid rsa t rp all banks precharge mode register set v ih v ih 55 high-z code
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 62 package dimensions hm5259165btd hm5259805btd hm5259405btd series (ttp-54da) hitachi code jedec eiaj weight (reference value) ttp-54da 0.58 g unit: mm *dimension including the plating thickness base material dimension 0.13 m 0.10 0.80 54 28 127 22.22 22.72 max 1.20 max 10.16 0.05 0.05 11.76 0.20 0 5 0.91 max *0.12 0.05 0.28 0.05 0.10 0.04 *0.30 0.50 0.10 0.45 0.80 + 0.10 0.05
hm5259165b/hm5259805b/hm5259405b-75/a6 data sheet e0118h10 63 cautions 1. elpida memory, inc. neither warrants nor grants licenses of any rights of elpida memory, inc. s or any third party s patent, copyright, trademark, or other intellectual property rights for information contained in this document. elpida memory, inc. bears no responsibility for problems that may arise with third party s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. elpida memory, inc. makes every attempt to ensure that its products are of high quality and reliability. however, contact elpida memory, inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by elpida memory, inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. elpida memory, inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating elpida memory, inc. product does not cause bodily injury, fire or other consequential damage due to operation of the elpida memory, inc. product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from elpida memory, inc.. 7. contact elpida memory, inc. for any questions regarding this document or elpida memory, inc. semiconductor products.

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